1.1
Features
The i.MX RT1040 processors are based on Arm Cortex-M7 Core Platform, which has the following features:
•
Supports single Arm Cortex-M7 Core with:
—
32 KB L1 Instruction Cache
—
32 KB L1 Data Cache
—
Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture
—
Support the Armv7-M Thumb instruction set
•
Integrated MPU, up to 16 individual protection regions
•
Tightly coupled GPIOs, operating at the same frequency as Arm Core
•
Up to 512 KB I-TCM and D-TCM in total
•
Frequency of 600 MHz
•
Cortex M7 CoreSight™ components integration for debug
•
Frequency of the core, as per Table 9.
The SoC-level memory system consists of the following additional components:
•
Boot ROM (128 KB)
•
On-chip RAM (512 KB)
—
512 KB OCRAM shared between ITCM/DTCM and OCRAM
•
External memory interfaces:
—
8/16-bit SDRAM, up to SDRAM-133/SDRAM-166
—
8/16-bit SLC NAND FLASH, with ECC handled in software
—
SD/eMMC
—
SPI NOR/NAND FLASH
—
Parallel NOR FLASH with XIP support
—
Two single/dual channel Quad SPI FLASH with XIP support
•
Timers and PWMs:
—
Two General Programmable Timers (GPT)
◦
4-channel generic 32-bit resolution timer for each
◦
Each support standard capture and compare operation
—
Four Periodical Interrupt Timers (PIT)
◦
Generic 32-bit resolution timer
◦
Periodical interrupt generation
Four Quad Timers (QTimer)
◦
4-channel generic 16-bit resolution timer for each
◦
Each support standard capture and compare operation
◦
Quadrature decoder integrated
Four FlexPWMs
◦
Up to 8 individual PWM channels per each
◦
16-bit resolution PWM suitable for Motor Control applications
Four Quadrature Encoder/Decoders