1 Features
• Four channels of transmitter and receiver with serial data
transfer rates of 2.488-3.1875Gbps/channel with full rate
and half-rate operations
• Up to 12.75Gbps data rate at full duplex
• User-controlled dual-speed operation (per channel) 2.488-
3.1875Gbps or 1.244-1.59Gbps
• IEEE 802.3ae-2002 10 GE and 10 GFC compliant
- XAUI, XGMII, and MDC/MDIO interfaces
• XGMII format 10-bit parallel input/output data
- Supports HSTL 1.8V and 2.5V SSTL_2
• Extensive configuration via 802.3-compliant MDC/MDIO
serial interface
• 8bit/10bit Encoding/Decoding per channel with selectable
parallel input/output data sizes
- Support optional 8b/10b encoder/decoder bypass
operation
• Integrated Equalization and Pre-emphasis
• De-skewing and channel-to-channel alignment options
• Low power, 250mW per channel typical
• Meets jitter requirements with significant margin
• Comma detection and synchronization, byte alignment
• Tx/Rx rate matching via IDLE insertion/deletion
• Receive signal detect and 16 levels of transmission
medium equalization
• CML transmit outputs with four levels of pre-emphasis
• Loopback
- Per-channel serial Tx-to-Rx and Rx-to-Tx parallel
internal loopback modes
• Single-ended/differential input Reference clock
• Double Data-Rate (DDR) mode, also optional SDR (Single
Data Rate) on transmitter
• Support both source-centered and source-simultaneous
clocking
• Long Run Length (512 bit) frequency lock ideal for
proprietary encoding schemes Transmit byte clock
schemes
- One Transmit Byte Clock (TBC) for each channel, or
one TBC for all four channels
• Received clock schemes
- Receive data aligned to local reference clock, to
recovered clock for each channel, or to recovered clock
for Channel A only
• Supports Built-In Self Test (BIST) and IEEE 1149.1 JTAG
• On-chip 25 series output terminations (XGMII side)
• Standard 0.18μm 1.8V CMOS technology
• 3.3V tolerant I/O