FEATURES
• Industry standard pinout and timing • All inputs, outputs and clocks are fully TTL compatible • Single +5V±10% power supply . • Low power, 15mW standby; 150mW active, typical Optional PAGE MODE access cycle . • Refresh modes: RAS-ONLY, CAS-BEFORE-RAS, and HIDDEN 256-cycle refresh distributed across 4ms Specifications guaranteed over full military DRAM temperature range (-55°C to +125°C) .

GENERAL DESCRIPTION
The AS4C4067 883C is a randomly accessed solid-state memory containing 262,144 bits organized in a 65,536 x 4 configuration. The 16 address bits are entered 8 bits at a time using RAS to latch the first 8 bits and CAS the latter 8 bits. If WE goes LOW after data reaches the output pins, the output pins are activated and retain the selected cell data as long as CAS and OE remain LOW (regardless of WE or RAS). This late WE pulse results in a READ-MODIFY-WRITE cycle. Data in is latched when WE strobes LOW. CAS may be toggled-in by holding RAS LOW to execute several faster READ, WRITE or READ-MODIFY-WRITE cycles within the RAS address defined page boundary. Returning RAS HIGH terminates the memory cycle and decreases chip current to a reduced standby level. Also, the chip is preconditioned for the next cycle during the RAS HIGH time. Memory cell data is retained in its correct state by maintaining power and executing a RAS (READ, WRITE, RAS-ONLY or HIDDEN REFRESH) cycle so that all 256 combinations of RAS addresses are executed at least every 4ms (regardless of sequence).