DESCRIPTION

The 74LVC1G07 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 or 5 V devices. This feature allows the use of this device as translator in a mixed 3.3 and 5 V environment. Schmitt trigger action at the input makes the circuit tolerant for slower input rise and fall time. The 74LVC1G07 provides the non-inverting buffer. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

FEATURES

• Wide supply voltage range from 1.65 to 5.5 V

• High noise immunity

• Complies with JEDEC standard:

– JESD8-7 (1.65 to 1.95 V)

– JESD8-5 (2.3 to 2.7 V)

– JESD8B/JESD36 (2.7 to 3.6 V).

• 24 mA output drive (VCC= 3.0 V)

• CMOS low power consumption

• Latch-up performance exceeds 250 mA

• Direct interface with TTL levels

• Inputs accept voltages up to 5 V

• Multiple package options

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V

• Specified from−40 to +85°C and−40 to +125°C.