Features
• SEMPER™ Flash and HYPERRAM™2.0 with HYPERBUS™ interface in multi-chip package (MCP)
- 1.8 V, 512Mb SEMPER™ Flash and 64Mb HYPERRAM™ 2.0 (S76HS512TC0)
- 3.0 V, 512Mb SEMPER™ Flash and 64Mb HYPERRAM™ 2.0 (S76HL512TC0)
- FBGA 24-ball, 8 × 8 × 1.2 mm packages
• HYPERBUS™ interface
- 1.8 V I/O (S76HS-TC0)
- 3.0 V I/O (S76HL-TC0)
- Chip select (CS#)
- 8-bit data bus (DQ[7:0])
- Data strobe (DS/RWDS)
• Bidirectional DS/mask
• Output at the start of all transactions to indicate refresh latency
• Output during read transactions as read DS
• Input during write transactions as write data mask (HYPERRAM™ only)
• Optional signals
- INT# output to generate external interrupt
• Busy to ready transition
- RSTO# output to generate system level power-on-reset (POR)
• User configurable RSTO# LOW period
• High-performance
- DDR
• Two data transfers per clock
- Up to 200 MHz clock rate (400-MBps) at 1.8 V VCC
- Up to 166 MHz clock rate (333-MBps) at 3.0 V VCC