DESCRIPTION
The TC5164(5)805BJ/BFT/BJS/BFTS is an EDO (hyper page) dynamic RAM organized as 8,388,608
words by 8 bits. TC5164(5)805BJ/BFT/BJS/BFTS utilizes TOSHIBA's CMOS silicon gate process
technology as well as advanced circuit techniques to provide wide operating margins, both internally
and to the system user. Multiplexed address inputs permit the TC5164(5)805BJ/BFT/BJS/BFTS to be
packaged in either a 32-pin plastic SOJ or a 32-pin plastic TSOP. The package size provides high
system bit densities and is compatible with widely available automated testing and insertion
equipment. Other features include a single power supply of 3.3V±0.3V tolerance and direct interfacing
with high performance logic families such as LVTTL.

FEATURES
8,388,608-word by 8-bit organization
Fast access time and cycle time
TC5164(5)805
TRAC
TAA
tCAC
tRC
tHPC
RAS Access Time
Column Address
Access Time
CAS Access Time
Cycle Time
Hyper Page Mode
Cycle Time
BJ/BFT/BJS/BFTS
-40
40ns
20ns
11ns
69ns
16ns
-50
50ns
25ns
Single power supply of 3.3V±0.3V
with a built-in VBB generator
• Low power dissipation (max)
Operating
306mW (TC5164805BJ/BFT/BJS/BFTS-40)
252mW (TC5164805BJ/BFT/BJS/BFTS-50)
432mW (TC5165805BJ/BFT/BJS/BFTS-40)
(TC5165805BJ/BFT/BJS/BFTS-50)
360mW
Standby : 1.8m W
0.72mW (S-version)
13ns
Outputs unlatched at cycle end, allowing two-dimensional
chip selection
84ns • Read-Modify-Write and EDO (Hyper Page mode) capability
• All inputs and outputs LVTTL-compatible
20ns
• Packages
BJ/BJS : SOJ32-P-400-1.27B, 1.27 grams
BFT/BFTS TSOPII 32-P-400-1.27B, 0.50grams