Features
• High-density, low-power Quantum™ compute fabric
• Built on TSMC 16 nm process
• 10-kbit high-speed, embedded SRAM, configurable as single-port RAM, simple dual-port
RAM, true dual-port RAM, or ROM
• High-performance DSP blocks for multiplication, addition, subtraction, accumulation,
and up to 15-bit variable-right-shifting
• Versatile on-chip clocking
— Low-skew global network supporting 32 clock or control signals
— Regional and local clock networks
— PLL support
• FPGA interface blocks
— High-voltage I/O (HVIO) (1.8, 2.5, 3.3 V)
— High-speed I/O (HSIO), configurable as:
– LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional), up to
1.5 Gbps
– MIPI lane I/O (DSI and CSI) in high-speed (HS) low-power (LP) modes, up to
1.5 Gbps
– Single-ended and differential I/O
— PLL
— Oscillator
• Flexible device configuration
— Standard SPI interface (active, passive, and daisy chain(1))
— JTAG interface
— Supports internal reconfiguration
• Single-event upset (SEU) detection feature
• Fully supported by the Efinity® software, an RTL-to-bitstream compiler
• Optional security feature
— Asymmetric bitstream authentication using RSA-4096
— Bitstream encryption/decryption using AES-GCM