GENERAL DESCRIPTION
The MC68HC05JB4 is a member of the low-cost, high-performance M68HC05 Family of 8-bit microcontroller units (MCUs). The M68HC05 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the popular M68HC05 central processing unit (CPU) and are available with a variety of subsystems, memory sizes and types, and package types.
The MC68HC05JB4 is specifically designed to be used in applications where a low speed (1.5Mbps) Universal Serial Bus (USB) interface is required.

FEATURES
• Industry standard M68HC05 CPU core
• Memory-mapped input/output (I/O) registers
• 3584 Bytes of user ROM
• 176 Bytes of user RAM (includes 64 byte stack)
• 19 Bidirectional I/O pins with the following added features:
    – PA[0:7]: Software enable Internal pull-up resistor (50kΩ typical)
    – PA[0:3]: Built-in schmitt triggered input level
    – Maskable as extra input sources for IRQ interrupt
    – Maskable Negative-Edge Only or Negative-Edge
    – and Low-Level Interrupt Capability
    – PA4: IRQ2 with built-in schmitt triggered input
    – PA[5:7]: 10mA Sink output drive
    – PA[6:7]: Maskable 10mA/25mA sink output drive
    – Software enable Slow Edge Pull Down Devices
    – PB[0:4]: Software enable Internal pull-up resistor (50kΩ typical)
    – Software enable Slow Edge Pull Down Devices
    – PB[0]: ICAP1 with built-in schmitt triggered input
    – PB[3:4]: AD[4:5]
    – PC[0:3]: AD[0:3]
• Fully compliant to Low Speed USB with 3 Endpoints:
    – 1 Control Endpoint (2x8 byte buffer)
    – 2 Interrupt Endpoints (1x8 byte buffer shared)
• 6-channel 8-bit Analog-to-Digital Converter (ADC)
• Multi-function Timer (MFT)
• 16-bit Timer with 1 input capture and 1 output compare
• Low Voltage Reset (LVR) Circuit
• Computer Operating Properly (COP) Watchdog Reset
• Provide a 3.3V ±10% DC Voltage for USB pull-up resistor
• Fully Static Operation with no Minimum Clock Speed
• Illegal Address Reset
• Power-Saving STOP and WAIT Modes
• Available in 28-Pin PDIP and 28-Pin SOIC packages

MASK OPTIONS
The following mask options are available:
• Enable PA0 to PA3 as extra IRQ interrupt sources.
• External interrupt pins (IRQ, PA0 to PA3): negative edge-triggered or negative edge- and low level-triggered.
• High current (25mA) output on PA6 and PA7.
• OSC: crystal/ceramic resonator start up delay, 4064 or 128 clock cycles.
• LVR: enabled or disabled.
• COP: enabled or disabled.