# CDC2536 3.3-V Phase-Lock Loop Clock Driver

## Features
️· Low output skew for clock distribution and generation
️· Operates at 3.3V VCC
️· Distributes one clock input to six outputs
️· Select input configures outputs to operate at one-half or double the input frequency
️· No external RC network required
️· On-chip series damping resistors
️· External feedback pin (FBIN) synchronizes outputs to the clock input
️· Suitable for synchronous DRAM and high-speed microprocessors
️· TTL-compatible inputs and outputs
️· Drives 50-Ω parallel-terminated transmission lines
️· Low power consumption due to EPIC-II B BiCMOS design
️· Reduces switching noise with distributed VCC and ground pins
️· Packaged in plastic 28-pin shrink small-outline package (SSOP)

## Description
The CDC2536 is a high-performance, low-skew, low-jitter clock driver utilizing a phase-lock loop (PLL) to align output clock signals with the input clock (CLKIN). It’s designed for synchronous DRAM and microprocessors operating from 50 MHz to 100 MHz or down to 25 MHz with half-frequency outputs. It drives 50-Ω transmission lines and features on-chip damping resistors, eliminating external components.

## Functional Details
️· Phase-Lock Loop (PLL): Precisely aligns output clocks to the input clock signal (CLKIN).
️· Feedback Input (FBIN): Requires one output clock to be fed back to FBIN for synchronization.
️· Select Input (SEL): Configures three outputs to operate at one-half or double the CLKIN frequency.
️· Output Enable (OE): Controls output state (active or high-impedance).
️· Test Input (TEST): Used for factory testing, bypasses PLL for testing.

## Electrical Characteristics
️· Operates at 3.3V VCC
️· TTL-compatible I/O

## Packaging
️· 28-pin SSOP
️· Available in Tape and Reel and Tube packaging.
️· Specific dimensions available for Tape & Reel and Tube including Length, Width, Height, SPQ, Reel diameter, and Tube dimensions.

## Applications
️· Synchronous DRAM
️· High-speed microprocessors
️· Clock distribution
️· Clock generation