## TNETE100PM: ThunderLAN PCI Fast Ethernet Controller The **TNETE100PM** is a highly integrated Ethernet controller chip developed by Texas Instruments (TI). It is part of the "ThunderLAN" family and was widely used in the late 1990s and early 2000s for 10/100 Mbps network interface cards (NICs) and embedded systems. --- ### 1. Key Technical Specifications The TNETE100PM acts as a bridge between the system’s PCI bus and the physical network layer. | Feature | Specification | | :--- | :--- | | **Data Rate** | 10 Mbps (Ethernet) and 100 Mbps (Fast Ethernet) | | **Host Interface** | PCI Local Bus Specification Revision 2.1 | | **Architecture** | 32-bit Bus Master DMA | | **PHY Interface** | Integrated 10Base-T PHY and MII (Media Independent Interface) | | **Package** | 144-pin PQFP (Plastic Quad Flat Pack) | | **Voltage** | 3.3V or 5.0V I/O tolerance | --- ### 2. Core Functional Components The internal architecture of the TNETE100PM is divided into several electronic blocks that handle different stages of data processing: #### A. PCI Interface Logic This section handles communication with the computer's CPU and memory. - **DMA Controller:** Uses Direct Memory Access to move data packets directly to system RAM without taxing the CPU. - **Configuration Registers:** Stores PCI-specific data such as Vendor ID, Device ID, and Interrupt settings. #### B. Media Access Controller (MAC) The MAC layer is responsible for the protocol logic: - **CSMA/CD:** Handles Carrier Sense Multiple Access with Collision Detection. - **Framing:** Adds headers, trailers, and CRC (Cyclic Redundancy Check) for error detection. - **Flow Control:** Supports full-duplex operation to prevent data loss. #### C. Physical Layer (PHY) & MII - **Integrated PHY:** Contains the analog circuitry to drive 10Base-T signals. - **MII Interface:** Allows the chip to connect to an external transceiver if specialized media (like Fiber Optics or HomePNA) is required. #### D. FIFO Memory Buffers The chip contains internal SRAM buffers (typically 2KB for Transmit and 2KB for Receive) to temporarily hold data packets, preventing "overflow" or "underrun" during high-speed transfers. --- ### 3. Pinout and Connectivity Categories The 144 pins on the TNETE100PM are generally grouped into these categories: 1. **PCI Bus Signals:** AD[31:0] (Address/Data), FRAME#, IRDY#, TRDY#, STOP#, and DEVSEL#. 2. **Network Interface:** TXP/TXN and RXP/RXN (Differential pairs for transmitting and receiving over twisted pair). 3. **EEPROM Interface:** Connects to a small external serial EEPROM (like a 93C46) to store the unique MAC address. 4. **Status LEDs:** Pins for Link, Activity, and Speed (10/100) indicators. 5. **Power/Ground:** Multiple VCC and GND pins for noise reduction and stable analog performance. --- ### 4. Legacy Context Today, the TNETE100PM is considered a **legacy component**. It is rarely found in modern consumer hardware but may still be encountered in: * Vintage computer restoration (Pentium II/III era). * Industrial legacy systems that require specific PCI-based networking. * Older embedded routers and print servers.