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  • ADM6328-31ARTZ-R7

  • AI
    The **ADM6328-31ARTZ-R7** is a precision voltage monitoring device manufactured by **Analog Devices**. It belongs to a family of microprocessor supervisory circuits designed to monitor power supply voltage levels in digital systems. --- ## 1. Core Technical Specifications The part number suffix (`31`) indicates its specific factory-preset threshold. | Feature | Specification | | :--- | :--- | | **Reset Threshold** | 3.08V (Typical) | | **Output Type** | Open-Drain (Active-Low) | | **Supply Current** | 1 µA (Ultra-low power) | | **Timeout Delay** | 100 ms (Minimum) | | **Package** | SOT-23-3 (3-lead Small Outline Transistor) | | **Operating Temp** | -40°C to +85°C | --- ## 2. Pin Configuration The device is designed for simplicity, using a standard 3-pin layout: 1. **GND**: Ground reference. 2. **RESET**: The output pin. It stays **LOW** when the monitored voltage is below the threshold or during the reset timeout period. Being "Open-Drain," it requires an external pull-up resistor. 3. **VCC**: The power supply input and the voltage being monitored. --- ## 3. Key Functional Features ### A. Power-On Reset (POR) When the system powers up, the ADM6328 ensures that the microprocessor does not start executing code until the supply voltage is stable. It holds the `RESET` line low for at least **100ms** after $V_{CC}$ crosses the 3.08V threshold. ### B. Brownout Protection If the voltage drops below the 3.08V threshold (a "brownout" condition), the device immediately pulls the `RESET` pin low to prevent the processor from malfunctioning or corrupting data. ### C. Ultra-Low Power Consumption With a typical supply current of only **1 µA**, this part is ideal for battery-operated devices where power efficiency is critical. ### D. Glitch Immunity The device is engineered to ignore fast, short-duration transients on the $V_{CC}$ line, preventing "false resets" caused by minor electrical noise. --- ## 4. Typical Application Circuit Because the output is **Open-Drain**, you must connect a resistor between the `RESET` pin and the $V_{CC}$ (or another logic rail). ```text [VCC] (3.3V Rail) | +-------+------- (Pull-up Resistor, e.g., 10kΩ) | | [Pin 3] [Pin 2] ------> To MCU Reset Pin (VCC) (RESET) | [Pin 1] (GND) | [Ground] ```
    ✨ Follow-up Questions
    • ⤷ What is the difference between an open-drain and a push-pull reset output?
    • ⤷ Can this part be used with a 5V logic system?
    • ⤷ How does the timeout delay affect the system startup time?