ST92F120 datasheet(219/324 Pages) STMICROELECTRONICS

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I2C BUS INTERFACE

I2C BUS INTERFACE (Cont’d)

Figure 106. I2C BUS Protocol

Any transfer can be done using either the I2C

registers directly or via the DMA.

If the transfer is to be done directly by accessing

the I2CDR, the interface waits (by holding the SCL

line low) for software to write in the Data Register

before transmission of a data byte, or to read the

Data Register after a data byte is received.

If the transfer is to be done via DMA, the interface

sends a request for a DMA transfer. Then it waits

for the DMA to complete. The transfer between the

interface and the I2C bus will begin on the next

rising edge of the SCL clock.

The SCL frequency (Fscl) generated in master

mode is controlled by a programmable clock divid-

er. The speed of the I2C interface may be selected

between Standard (0-100KHz) and Fast (100-

400KHz) I2C modes.

10.7.4 I2C State Machine

To enable the interface in I2C mode the I2CCR.PE

bit must be set twice as the first write only acti-

vates the interface (only the PE bit is set); and the

bit7 of I2CCR register must be cleared.

The I2C interface always operates in slave mode

(the M/SL bit is cleared) except when it initiates a

transmission or a receipt sequencing (master

mode).

The multimaster function is enabled with an auto-

matic switch from master mode to slave mode

when the interface loses the arbitration of the I2C

bus.

10.7.4.1 I2C Slave Mode

As soon as a start condition is detected, the

address word is received from the SDA line and

sent to the shift register; then it is compared with

the address of the interface or the General Call

address (if selected by software).

Note: In 10-bit addressing mode, the comparison

includes the header sequence (11110xx0) and the

two most significant bits of the address.

Header (10-bit mode) or Address (both 10-bit

and 7-bit modes) not matched: the state

machine is reset and waits for another Start

condition.

Header matched (10-bit mode only): the

interface generates an acknowledge pulse if the

ACK bit of the control register (I2CCR) is set.

Address matched: the I2CSR1.ADSL bit is set

and an acknowledge bit is sent to the master if

the I2CCR.ACK bit is set. An interrupt request

occurs if the I2CCR.ITE bit is set. Then the SCL

line is held low until the microcontroller reads

the I2CSR1 register (see Figure 3 Transfer

sequencing EV1).

SCL

SDA

MSB

ACK

STOP

START

CONDITION

VR02119B

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