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ST92F120 датащи(PDF) 115 Page - STMicroelectronics |
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ST92F120 датащи(HTML) 115 Page - STMicroelectronics |
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115 / 324 page ![]() 115/324 ST92F120 - EXTERNAL MEMORY INTERFACE (EXTMI) 8.3 REGISTER DESCRIPTION EXTERNAL MEMORY REGISTER 1 (EMR1) R245 - Read/Write Register Page: 21 Reset value: 1000 0000 (80h) Bit 7 = Reserved. Bit 6 = MC: Mode Control. 0: AS, DS and RW pins have the standard ST9 meaning. 1: AS pin becomes ALE, Address Load Enable (AS inverted); Thus Memory Adress, Read/ Write signals are valid whenever a falling edge of ALE occurs. DS becomes OEN, Output ENable: it has the standard ST9 meaning during external read op- erations, but is forced to “1” during external write operations. RW pin becomes WEN, Write ENable: it follows the standard ST9 DS meaning during external write operations, but is forced to “1” during ex- ternal read operations. Bit 5 = DS2EN: Data Strobe 2 enable. 0: The DS2 pin is forced to “1” during the whole memory cycle. In this case, access to upper or lower memory is controlled by the DS pin. 1: If the lower memory block is addressed, the DS2 pin follows the standard ST9 DS meaning (if MC=0) or it becomes OEN (if MC=1). The DS pin is forced to 1 during the whole memory cy- cle. If the upper memory block is used, DS2 is forced to “1” during the whole memory cycle. The DS pin behaviour is not modified. Refer to Figure 57 Bit 4 = ASAF: Address Strobe as Alternate Func- tion. Depending on the device, AS can be either a ded- icated pin or a port Alternate Function. This bit is used only in the second case. 0: AS Alternate function disabled. 1: AS Alternate Function enabled. Bit 2 = ETO: External toggle. 0: The external memory interface pins (AS, DS, DS2, RW, Port0, Port1) toggle only if an access to external memory is performed. 1: When the internal memory protection is dis- abled (mask option available on some devices only), the above pins (except DS and DS2 which never toggle during internal memory accesses) toggle during both internal and external memory accesses. Bit 1 = BSZ: Bus size. 0: All the I/O ports including the external memory interface pins use smaller, less noisy output buffers. This may limit the operation frequency of the device, unless the clock is slow enough or sufficient wait states are inserted. 1: All the I/O ports including the external memory interface pins (AS, DS, DS2, R/W, Port 0, 1) use larger, more noisy output buffers . Bit 0 = Reserved. CAUTION: External memory must be correctly ad- dressed before and after a write operation on the EMR1 register. For example, if code is fetched from external memory using the standard ST9 ex- ternal memory interface configuration (MC=0), setting the MC bit will cause the device to behave unpredictably. 70 x MC DS2EN ASAF x ETO BSZ X 9 |
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