ST72324BL datasheet(132/151 Pages) STMICROELECTRONICS

132 / 151 page

ST72F324L, ST72324BL

132/151

12.12 10-BIT ADC CHARACTERISTICS

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.

Figure 77. RAIN max. vs fADC with CAIN=0pF

Figure 78. Recommended CAIN & RAIN values.

Notes:

1. When VAREF and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.

2. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k

Ω). Data

based on characterization results, not tested in production.

3. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-

pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.

4. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and

decreased to allow the use of a larger serial resistor (RAIN).

5.The analog inputs of ROM devices are designed to be negative current tolerant. On Flash devices, injecting negative

current on any of the analog input pins significantly reduces the accuracy of any conversion being performed on any an-

alog input.

Analog pins can be protected against negative injection by adding a Schottky diode (pin to ground). Injecting negative

current on digital input pins degrades ADC accuracy especially if performed on a pin close to the analog input pins.

Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 12.8 does not affect the ADC

accuracy.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fADC

ADC clock frequency

0.4

MHz

VAREF

Analog reference voltage 1)

VDD

VAIN

Conversion voltage range 2)

VSSA

VAREF

Ilkg

Positive input leakage current for analog

input

-40°C

≤T

A≤85°C range

µA

ROM devices: negative input leakage

current on analog pins 5)

VIN<VSS, | IIN |< 400µA

on adjacent analog pin

µA

RAIN

External input impedance

see

Figure 77

and

Figure

782)3)4)

Ω

CAIN

External capacitor on analog input

fAIN

Variation freq. of analog input signal

CADC

Internal sample and hold capacitor

tADC

Conversion time (Sample+Hold)

fCPU=4MHz, SPEED=0 fADC=1MHz

µs

tADC

- No of sample capacitor loading cycles

- No. of Hold conversion cycles

1/fADC

010

CPARASITIC (pF)

1 MHz

0.1

100

1000

0.01

0.1

fAIN(KHz)

Cain 10 nF

Cain 22 nF

Cain 47 nF

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