MPXM2102AS datasheet(461/670 Pages) MOTOROLA

461 / 670 page

AN1518

3–315

Motorola Sensor Device Data

www.motorola.com/semiconductors

THE MICROCONTROLLER

The microcontroller for this application requires input

capture and output compare timer channels. The output

capture pin is programmed to output the pulse train that drives

the ramp generator, and the input capture pin detects edge

transitions to measure the PWM output pulse width.

Since software controls the entire system, a calibration

routine may be implemented that allows an adjustment of the

frequency and pulse width of the pulse train until the desired

ramp waveform is obtained. Depending on the speed of the

microcontroller, additional constraints on the minimum and

maximum PWM output pulse widths may apply. For this

design, the software latency incurred to create the pulse train

at the output compare pin is approximately 40

µs.

Consequently, the microcontroller cannot create a pulse train

with a positive pulse width of less than 40

µs. Also, the

software that measures the PWM output pulse width at the

input capture pin requires approximately 20

µs to execute.

Referring to Figure 5, the software interrupt that manipulates

the pulse train always occurs near an edge detection on the

input capture pin (additional software interrupt). Therefore, the

minimum PWM output pulse width that can be accurately

detected is approximately 60

µs (20 µs + 40 µs). This

constrains the minimum and maximum pulse widths more

than the slew rate of the comparator which was discussed

earlier (refer to Figure 4).

Figure 4. Desired Relationship Between the Ramp Waveform

and Pressure Sensor Voltage Spans

∆V Sets Minimum

Pulse Width (60

µs)

VSFS

VSOFF

∆V Sets Maximum

Pulse Width

(Period – 60

µs)

An additional consideration is the resolution of the PWM

output. The resolution is directly related to the maximum

frequency of the pulse train. In our design, 512

µs are required

to obtain at least 8–bit resolution. This is determined by the

fact that a 4 MHz crystal yields a 2 MHz clock speed in the

microcontroller. This, in turn, translates to 0.5

µs per clock tick.

There are four clock cycles per timer count. This results in 2

µs

per timer count. Thus, to obtain 256 timer counts (or 8–bit

resolution), the difference between the zero pressure and full

scale pressure PWM output pulse widths must be at least

512

µs (2 µs x 256). But since an additional 60 µs is needed

at both pressure extremes of the output waveform, the total

period must be at least 632

µs. This translates to a maximum

frequency for the pulse train of approximately 1.6 kHz. With

this frequency, voltage span of the ramp generator, and value

of current charging the capacitor, the minimum capacitor value

may be calculated with Equation 1.

To summarize:

The MC68HC705P9 runs off a 4 MHz crystal. The

microcontroller internally divides this frequency by two to yield

an internal clock speed of 2 MHz.

2MHz

+§

0.5

clock cycle

And,

4 clock cycles = 1 timer count.

Therefore,

4 clock cycles

timer count

0.5

clock cycle

timer count

For 8–bit resolution,

timer count

256 counts

+ 512 ms

Adding a minimum of 60

µs each for the zero and full scale

pressure pulse widths yields

512

µs + 60 µs + 60 µs = 632 µs,

which is the required minimum pulse train period to drive the

ramp generator.

Translating this to frequency, the maximum pulse train

frequency is thus

632

ms +

1.58 kHz .

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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