ST7MC1K2-Auto datasheet(300/371 Pages) STMICROELECTRONICS

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Thus, it is mandatory to read the ADCDRMSB just after reading the ADCDRLSB. Otherwise

the ADCDR register is not updated until the ADCDRMSB is read.

10.8.4

Low power modes

Note:

The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced

power consumption when no conversion is needed.

10.8.5

Interrupts

10.8.6

Control/status register (ADCCSR)

Table 171.

Effect of low power modes on A/D converter

Mode

Description

Wait

No effect on A/D converter

Halt

A/D converter disabled.

After wake up from Halt mode, the A/D converter requires a stabilization time

tSTAB (seeSection 12: Electrical characteristics) before accurate conversions

can be performed.

Table 172.

A/D converter interrupt control/wake-up capability

Interrupt event

Event flag

Enable control

bit

Exit from Wait

Exit from Halt

End of Conversion

EOC

ADCIE(1)

The ADCIE bit is in the MCCBCR register (see Section 6.6.7: MCC control status register (MCCSR) on

page 56)

Yes

ADCCSR

Reset value: 0000 0000 (00h)

654

EOC

PRSC[1:0]

ADON

CS[3:0]

R/W

Table 173.

ADCCSR register description

Bit

Name

Function

7EOC

End of conversion

This bit is set by hardware. It is cleared by software reading the ADCDRMSB

0: Conversion is not complete

1: Conversion complete

6:5 PRSC[1:0]

ADC clock prescaler selection

These bits are set and cleared by software:

00: fADC =4MHz

01:fADC =2MHz

10: fADC =1MHz

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