ST7MC1K2-Auto datasheet(153/371 Pages) STMICROELECTRONICS

153 / 371 page

Obsolete

Product(s)

- Obsolete

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ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto

On-chip peripherals

153/371

SCI control register 1 (SCICR1)

3OR

Overrun error

The OR bit is set by hardware when the word currently being received in the shift

interrupt is generated if RIE = 1 in the SCICR2 register. It is cleared by a software

sequence (an access to the SCISR register followed by a read to the SCIDR register).

0: No Overrun error

1: Overrun error detected

Note: When this bit is set, RDR register contents are not lost but the shift register is

overwritten.

2NF

Character noise flag

This bit is set by hardware when noise is detected on a received character. It is

cleared by a software sequence (an access to the SCISR register followed by a read

to the SCIDR register).

0: No noise

1: Noise is detected

Note: This bit does not generate interrupt as it appears at the same time as the RDRF

bit which itself generates an interrupt.

1FE

Framing error

This bit is set by hardware when a desynchronization, excessive noise or a break

character is detected. It is cleared by a software sequence (an access to the SCISR

0: No framing error

1: Framing error or break character detected

Note: This bit does not generate an interrupt as it appears at the same time as the

RDRF bit which itself generates an interrupt. If the word currently being transferred

causes both a frame error and an overrun error, it is transferred and only the OR bit is

set.

0PE

Parity error

This bit is set by hardware when a byte parity error occurs (if the PCE bit is set) in

receiver mode. It is cleared by a software sequence (a read to the status register

followed by an access to the SCIDR data register). An interrupt is generated if PIE = 1

in the SCICR1 register.

0: No parity error

1: Parity error detected

SCICR1

Reset value: x000 0000 (x0h)

654

SCID

WAKE

PCE(1)

This bit has a different function in LIN mode; please refer to Section 10.5.10: LIN mode registers

PIE

R/W

Table 62.

SCISR register description (continued)

Bit Name

Function

Obsolete

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Product(s)

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