ST7MC1K2-Auto datasheet(122/371 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto

122/371

Control/status register (CSR)

The 3 least significant bits are not used.

1IEDG2

Input edge 2

This bit determines which type of level transition on the ICAP2 pin triggers the

capture.

0: A falling edge triggers the capture

1: A rising edge triggers the capture

EXEDG

External clock edge

This bit determines which type of level transition on the external clock pin EXTCLK

triggers the counter register.

0: A falling edge triggers the counter register

1: A rising edge triggers the counter register

CSR

Reset value: 0000 0000 (00h)

654

ICF1

OCF1

TOF

ICF2

OCF2

TIMD

Reserved

Table 52.

CSR register description

Bit Name

Function

ICF1

Input capture flag 1

0: No input capture (reset value)

1: An input capture has occurred on the ICAP1 pin or the counter has reached the

OC2R value in PWM mode. To clear this bit, first read the SR register, then read or

write the low byte of the IC1R (IC1LR) register.

6OCF1

Output compare flag 1

0: No match (reset value)

1: The content of the free running counter has matched the content of the OC1R

the OC1R (OC1LR) register.

5TOF

Timer overflow flag

0: No timer overflow (reset value)

1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first

read the SR register, then read or write the low byte of the CR (CLR) register.

Note: reading or writing the ACLR register does not clear TOF.

4ICF2

Input capture flag 2

0: No input capture (reset value)

1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR

Table 51.

CR2 register description (continued)

Bit

Name

Function

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