ST7MC1K2 datasheet(101/371 Pages) STMICROELECTRONICS

101 / 371 page

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ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto

On-chip peripherals

101/371

PWM duty cycle registers (PWMDCRx)

ART input capture control/status register (ARTICCSR)

Table 41.

PWMCR register description

Bit

Name

Function

7:4 OE[3:0]

PWM output enable

These bits are set and cleared by software. They enable or disable the PWM output

channels independently acting on the corresponding I/O pin.

0: PWM output disabled

1: PWM output enabled

3:0 OP[3:0]

PWM output polarity

These bits are set and cleared by software. They independently select the polarity

of the four PWM output signals (see Table 42).

Table 42.

PWM output signal polarity selection

PWMx output level

OPx(1)

When an OPx bit is modified, the PWMx output signal polarity is immediately reversed.

Counter < OCRx

Counter > OCRx

PWMDCRx

Reset value: 0000 0000 (00h)

654

DC[7:0]

R/W

Table 43.

PWMDCRx register description

Bit

Name

Function

7:0 DC[7:0]

Duty cycle data

These bits are set and cleared by software. A PWMDCRx register is associated with

the OCRx register of each PWM channel to determine the second edge location of

the PWM signal (the first edge location is common to all channels and given by the

ARTARR register). These PWMDCR registers allow the duty cycle to be set

independently for each PWM channel.

ARTICCSR

Reset value: 0000 0000 (00h)

654

Reserved

CS[2:1]

CIE[2:1]

CF[2:1]

R/W

Obsolete

Product(s)

- Obsolete

Product(s)

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