TNETV2501INPGF datasheet(139/197 Pages) TI1

139 / 197 page

Electrical Specifications

139

December 2002 − Revised November 2008

SPRS206K

Transmission Line

4.0 pF

1.85 pF

Z0 = 50

Ω

(see note)

Tester Pin Electronics

Data Sheet Timing Reference Point

Output

Under

Test

NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects

must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.

The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from

the data sheet timings.

Ω

3.5 nH

Device Pin

(see note)

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

Figure 5−1. 3.3-V Test Load Circuit

5.5

Timing Parameter Symbology

Timing parameter symbols used in the timing requirements and switching characteristics tables are created

in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related

terminology have been abbreviated as follows:

Lowercase subscripts and their meanings:

Letters and symbols and their meanings:

access time

High

cycle time (period)

Low

delay time

Valid

dis

disable time

High impedance

enable time

fall time

hold time

rise time

setup time

transition time

valid time

pulse duration (width)

Unknown, changing, or don’t care level

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