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PC97307VUL датащи(PDF) 105 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали PC97307VUL
подробное описание детали  PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
PDF  218 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
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PC97307VUL датащи(HTML) 105 Page - National Semiconductor (TI)

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First Command Phase Byte, Bit6-Write Track Number
(WNR)
0 - Read the existing track number.
The result phase byte already contains the track
number, and the third byte in the command phase
is a dummy byte.
1 - Change the track number by writing a new value to
the result phase byte.
Second Command Phase Byte
Bits 1,0 - Logical Drive Select (DS1,0)
These bits indicate which logical drive is active. See
“Bits 1,0 - Logical Drive Select (DS1,0)” on page 90.
00 - Drive 0 is selected.
01 - Drive 1 is selected.
10 - If four drives are supported, or drives 2 and 0 are
exchanged, drive 2 is selected.
11 - If four drives are supported, drive 3 is selected.
Bit 2 - Most Significant Byte (MSB)
This bit, together with bits 1,0, determines the byte to
read or write. See also Table 5-23.
0 - Least significant byte of the track number.
1 - Most significant byte of the track number.
TABLE 5-23. Defining Bytes to Read or Write Using
SET TRACK
Execution Phase
Internal register is read or written.
Result Phase
This byte is one byte of the track number that was read or
written, depending on the value of WNR in the first com-
mand byte.
MSB
DS1
DS0
Byte to Read or Write
210
0
0
0
Drive 0 (LSB)
1
0
0
Drive 0 (MSB)
0
0
1
Drive 1 (LSB)
1
0
1
Drive 1 (MSB)
0
1
0
Drive 2 (LSB)
1
1
0
Drive 2 (MSB)
0
1
1
Drive 3 (LSB)
1
1
1
Drive 3 (MSB)
76543210
Byte of Present Track Number(PTR)
5.7.21
The SPECIFY Command
The SPECIFY command sets initial values for the following
time periods:
• The delay before command processing starts, formerly
called Motor On Time (MNT)
• The delay after command processing terminates, for-
merly called Motor Off Time (MFT)
• The interval step rate time.
The FDC uses the Digital Output Register (DOR) to enable
the drive and motor select signals. See also, “Digital Output
Register (DOR), Offset 02h” on page 71.
The delays may be used to support the
µPD765, i.e., to in-
sert delays from selection of a drive motor until a read or
write operation starts, and from termination of a command
until the drive motor is no longer selected, respectively.
The parameters used by this command are undefined after
power up, and are unaffected by any reset. Therefore, soft-
ware should always issue a SPECIFY command as part of
an initialization routine to initialize these parameters.
Termination of this command does not generate an inter-
rupt.
Command Phase
.
Second Command Phase Byte
Bits 3-0 - Delay After Processing Factor
These bits specify a factor that is multiplied by a con-
stant to determine the delay after command processing
ends, i.e., from termination of a command until the drive
motor is no longer selected.
The value of the Motor Timer Values (TMR) bit (bit 7) of
the second command phase byte in the MODE com-
mand determines which group of constants and delay
ranges to use. See “Bit 7 - Motor Timer Values (TMR)”
on page 93.
The specific constant that will be multiplied by this factor
to determine the actual delay after processing for each
data transfer rate is shown in Table 5-24.
Use the smallest possible value for this factor, except 0,
i.e., 1. If this factor is 0, the value16 is used.
Bits 7-4 - STEP Time Interval Value (SRT)
These bits specify a value that is used to calculate the
time interval between successive STEP signal pulses
during a SEEK, IMPLIED SEEK, RECALIBRATE, or
RELATIVE SEEK command.
Table 5-26 shows how this value is used to calculate the
actual time interval.
76543210
00000011
Step Rate Time (SRT)
Delay After Processing
Delay Before Processing
DMA



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