PC87309VLJ datasheet(190/192 Pages) NSC

190 / 192 page

190

Glossary

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Full-IR mode

In this mode, the PC87309 decodes address lines

A0-A10, and UART2 is a fully featured UART with

IR. The mode is conﬁgured during reset, via CFG0

strap pin.

IER

The Interrupt Enable Register for the UARTs.

Infrared.

IRCFG1, IRCFG3 and IRCFG4

Infrared module Conﬁguration registers for UART2.

IRCR1, IRCR2 and IRCR3

Infrared Module Control Registers 1, 2 and 3 for

UART2.

IrDA

Infrared Data Association.

IRRXDC

Infrared Receiver Demodulator Control register for

the UART2. (Logical Device 2, bank 7, offset 00h.)

IRTXMC

Infrared Transmitter Modulator Control register for

UART2.

LBGD(H) and LBGD(L)

Legacy Baud rate Generator Divisor port (High and

Low bytes) for the UARTs.

LCR

Link Control Register for the UARTs.

Legacy

Usually refers to older devices or systems that are

not Plug and Play compatible.

Legacy Mode

In this mode, the interrupts and the base addresses

of the FDC, UARTs, KBC and the Parallel Port of

the PC87309 are conﬁgured as in earlier SuperI/O

chips.

LFSR

The Linear Feedback Shift Register. This register is

used to prepare the chip for operation in Plug and

Play (PnP) mode.

LSR

Link Status Register for the UARTs.

MCR

Modem Control Register for the UARTs.

MSR

Two expressions:

1. Main Status Register of the FDC.

2. Modem Status Register for the UARTs.

Non-Extended UART Operation Modes

These UART operation modes support only UART

operations that are standard for 15450 or 16550A

devices.

PIO

Programmable Input/Output.

P_MDR

Pipeline Mode Register for the UARTs.

Plug and Play

A design philosophy and a set of speciﬁcations that

describe hardware and software changes to the PC

and its peripherals that automatically identify and

arbitrate resource requirements among all devices

and buses on the system. Plug and Play is abbrevi-

ated as PnP.

Power Management.

PME

Power Management Event.

PMC1, PMC2 and PMC3

Power Management Control registers.

PnP

Plug and Play.

PnP Mode

In this mode, the interrupts, the DMA channels and

the base address of the FDC, UARTs, KBC, GPIO

and the Parallel Port of the PC87309 are fully Plug

and Play.

PP Confg0

Internal conﬁguration register of the Parallel Port in

Extended Capabilities Port (ECP) modes.

Precompensation

Also called write precompensation, is a way of pre-

conditioning the

WDATA output signal to adjust for

the effects of bit shift on the data as it is written to

the disk surface.

RBR

Receiver Buffer Register for the UARTs read opera-

tions.

RCCFG

Consumer Remote Control Conﬁguration register

for UART2.

RLC

Run Length Count byte for parallel ports.

RLE

Run Length Expander for parallel ports.

RXFLV

Reception FIFO Level for the UARTs.

SCI

System Control Interrupt.

SCR

Scratch Register for the UARTs.

SH_FCR

Shadow of the FIFO Control Register (FCR) for the

UARTs.

SH_LCR

Shadow of the Line Control Register (LCR) for the

UARTs for read operations.

Sharp IR Mode

In this mode, the PC87309 supports a Sharp Infra-

red interface.

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