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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PC87303 датащи(PDF) 103 Page - National Semiconductor (TI) |
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PC87303 датащи(HTML) 103 Page - National Semiconductor (TI) |
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103 / 114 page  100 Electrical Characteristics (Continued) 1026 Receiver Timing Symbol Parameter Conditions Min Max Units tRAI Delay from Active Edge of RD to Reset IRQ 78 ns tRINT Delay from Inactive Edge of RD (RD LSR) to Reset IRQ 55 ns tSCD Delay from RCLK to Sample Time (Note 1) 41 ns tSINT Delay from Stop Bit to Set Interrupt 2 Baud Out Cycle Note 1 This is an internal timing specification and is therefore not tested TLC12074 – 87 FIGURE 10-7 Sample Clock Timing TLC12074 – 64 FIGURE 10-8 Receiver Timing TLC12074 – 65 Note 1 If SCR0 e 1 then tSINT e 3 RCLKs For a Timeout Interrupt tSINT e 8 RCLKs FIGURE 10-9 FIFO Mode Receiver Timing 103 |
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