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AT89C51CC03U-RDTIM датащи(PDF) 167 Page - ATMEL Corporation |
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AT89C51CC03U-RDTIM датащи(HTML) 167 Page - ATMEL Corporation |
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167 / 195 page ![]() 167 AT89C51CC03 4182I–CAN–06/05 Table 115. IPH1 Register IPH1 (S:F7h) Interrupt High Priority Register 1 Reset Value = XXXX 0000b 76 543 210 - - - - SPIH POVRH PADCH PCANH Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3 SPIH SPI Interrupt Priority Level Most Significant bit SPIH SPIL Priority level 0 0 Lowest 0 1 1 0 1 1 Highest 2POVRH Timer overrun Interrupt Priority Level Most Significant bit POVRH POVRL Priority level 0 0 Lowest 0 1 1 0 1 1 Highest 1PADCH ADC Interrupt Priority Level Most Significant bit PADCH PADCL Priority level 0 0 Lowest 0 1 1 0 1 1 Highest 0 PCANH CAN Interrupt Priority Level Most Significant bit PCANH PCANL Priority level 0 0 Lowest 0 1 1 0 1 1 Highest |
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