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AT89C51CC03U-RDTIM датащи(PDF) 132 Page - ATMEL Corporation |
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AT89C51CC03U-RDTIM датащи(HTML) 132 Page - ATMEL Corporation |
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132 / 195 page ![]() 132 AT89C51CC03 4182I–CAN–06/05 Functional Description Figure 58 shows a detailed structure of the SPI Module. Figure 58. SPI Module Block Diagram Operating Modes The Serial Peripheral Interface can be configured in one of the two modes: Master mode or Slave mode. The configuration and initialization of the SPI Module is made through two registers: • The Serial Peripheral Control register (SPCON) • The Serial Peripheral Status and Control Register (SPSCR) Once the SPI is configured, the data exchange is made using: • The Serial Peripheral DATa register (SPDAT) During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sam- pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows individual selection of a Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities. Shift Register 0 1 2 3 4 5 6 7 Internal Bus Pin Control Logic MISO MOSI SCK M S Clock Logic SPI Interrupt 8-bit bus 1-bit signal SS FCLK Receive Data Register SPDAT SPI Control Transmit Data Register -MODF SPIF OVR SPTE UARTM SPTEIE MODFIE SPSCR SPEN MSTR SPR2 SSDIS CPOL CPHA SPR1 SPR0 SPCON Request PERIPH |
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