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MB91F577CPMC датащи(PDF) 137 Page - Cypress Semiconductor

номер детали MB91F577CPMC
подробное описание детали  32-bit RISC, load/store architecture, 5-stage pipeline
PDF  163 Pages
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производитель  CYPRESS [Cypress Semiconductor]
домашняя страница  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

MB91F577CPMC датащи(HTML) 137 Page - Cypress Semiconductor

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Document Number: 002-04725 Rev.*A
Page 137 of 163
MB91570 Series
Bit setting: ESCR: SCES = 1, ECCR: SCDE = 1
(TA: Recommended operating conditions, VCC5 = 5.0V±10%, VCCE = 5.0V±10%, VSS = AVSS = 0.0V)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Remarks
Min
Max
Serial clock cycle time
tSCYC
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7
–
5tCPP
–
ns
Internal shift clock
Mode:
CL=80pF+1 • TTL
SCK
↓→
SOT delay time
tSLOVI
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7,
SOT2,SOT3,
SOT4,SOT5,
SOT6,SOT7
-50
+50
ns
Valid SIN
→
SCK
↑ setup time
tIVSHI
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7,
SIN2,SIN3,
SIN4,SIN5,
SIN6,SIN7
tCPP+80
–
ns
SCK
↑→
Valid SIN hold time
tSHIXI
0
–
ns
SOT
→
SCK
↑ delay time
tSOVHI
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7,
SOT2,SOT3,
SOT4,SOT5,
SOT6,SOT7
3tCPP-70
–
ns
Notes:
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operation clock used and other parameters.
Refer to Hardware Manual for details.
Internal shift clock mode
2.4V
2.4V
0.8V
0.8V
SINx
SOTx
SCKx
t
SCYC
t
SHIXI
t
IVSHI
VIL
V
IH
V
IL
VIH
2.4V
0.8V
t
SLOVI
t
SOVHI
2.4V



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