LAN9250 datasheet(192/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 192

 2015 Microchip Technology Inc.

11.15 Host MAC Control and Status Registers

This section details the indirectly addressable Host MAC System CSRs. These registers are located in the Host MAC

and are accessed indirectly via the system CSRs. Table 11-17 lists Host MAC registers that are accessible through the

indexing method using the Host MAC CSR Interface Command Register (MAC_CSR_CMD) and Host MAC CSR Inter-

face Data Register (MAC_CSR_DATA).

The Host MAC registers allow configuration of the various Host MAC parameters including the Host MAC address, flow

control, multicast hash table, and wake-up configuration. The Host MAC CSRs also provide serial access to the PHY

via the registers HMAC_MII_ACC and HMAC_MII_DATA. These registers allow access to the 10/100 Ethernet PHY reg-

isters.

TABLE 11-17: HOST MAC ADDRESSABLE REGISTERS

Address

(Indirect)

00h

Reserved for Future Use (RESERVED)

01h

Host MAC Control Register (HMAC_CR)

02h

Host MAC Address High Register (HMAC_ADDRH)

03h

Host MAC Address Low Register (HMAC_ADDRL)

04h

Host MAC Multicast Hash Table High Register (HMAC_HASHH)

05h

Host MAC Multicast Hash Table Low Register (HMAC_HASHL)

06h

Host MAC MII Access Register (HMAC_MII_ACC)

07h

Host MAC MII Data Register (HMAC_MII_DATA)

08h

Host MAC Flow Control Register (HMAC_FLOW)

09h

Host MAC VLAN1 Tag Register (HMAC_VLAN1)

0Ah

Host MAC VLAN2 Tag Register (HMAC_VLAN2)

0Bh

Host MAC Wake-up Frame Filter Register (HMAC_WUFF)

0Ch

Host MAC Wake-up Control and Status Register (HMAC_WUCSR)

0Dh

Host MAC Checksum Offload Engine Control Register (HMAC_COE_CR)

0Eh

Host MAC EEE Time Wait TX System Register (HMAC_EEE_TW_TX_SYS)

0Fh

Host MAC EEE TX LPI Request Delay Register (HMAC_EEE_TX_LPI_REQ_DELAY)

10h-FFh

Reserved for Future Use (RESERVED)

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