LAN9250 datasheet(102/421 Pages) MICROCHIP

102 / 421 page

LAN9250

DS00001913A-page 102

 2015 Microchip Technology Inc.

9.5.5

TX AND RX FIFO ACCESS

9.5.5.1

TX and RX Status FIFO Peek Address Access

Normal read access to the TX or RX Status FIFO causes the FIFO to advance to its next entry.

For access to the TX and RX Status FIFO Peek addresses, FIFO does not advance to its next entry.

9.5.5.2

Index Register Bypass FIFO Access

In addition to the indexed access, the Index Registers can be bypassed and the FIFOs accessed at address 18h-1Bh.

At this address, host write operations are to the TX Data FIFO and host read operations are from the RX Data FIFO .

There is no associated Index Register.

Index Register Bypass and FIFO Direct Select accesses share the same read and write BYTE / WORD counters and

the same write DWORD assembly registers.

The endianness of FIFO accesses using this method is specified by the FIFO Endianness bit in the Host Bus Interface

Configuration Register.

9.5.5.3

FIFO Direct Select Access

In addition to the indexed access, a FIFO Direct Select signal is provided. This allows the host system to access the TX

and RX Data FIFOs as if they were a large flat address space. When the FIFOSEL input is active, all host write opera-

tions are to the TX Data FIFO and all host read operations are from the RX Data FIFO. The lower host address signals

are decoded in order to select the proper BYTE or WORD and to delimit DWORDs during a burst access.

Burst access is supported when reading the RX Data FIFO. With the FIFOSEL input active, CS and RD (or ENB with

RD_WR indicating read) may be left active while the lower address lines toggle. Each change of the lower address bits

provides the next WORD or BYTE of data. The HBI performs an internal FIFO pop (read cycle) when it detects that a

DWORD boundary has been crossed (A[2] has toggled).

The endianness of FIFO Direct Select accesses is specified by the FIFO Endianness bit in the Host Bus Interface Con-

figuration Register.

9.5.6

INDEXED ADDRESS MODE FUNCTIONAL TIMING DIAGRAMS

The following timing diagrams illustrate example indexed (non-multiplexed) addressing mode read and write cycles for

various configurations and bus sizes. These diagrams do not cover every supported host bus permutation, but are

selected to detail the main configuration differences (bus size, Configuration/Index/Data/FIFO-Direct cycles) within the

indexed addressing mode of operation.

The following should be noted for the timing diagrams in this section:

• The diagrams in this section depict active-high CS, RD, and WR signals. The polarities of these signals are select-

able via the HBI_cs_polarity_strap, HBI_rd_rdwr_polarity_strap, and HBI_wr_en_polarity_strap, respectively.

Refer to Section 9.3, "Control Line Polarity," on page 74 for additional details.

• The diagrams in this section depict little endian byte ordering. However, configurable big and little endianess are

supported via the endianness bits in the Host Bus Interface Configuration Register. Endianess changes only the

order of the bytes involved, and not the overall timing requirements. Refer to Section 9.5.4.3, "Host Endianness,"

on page 99 for additional information.

• The diagrams in this section utilize RD and WR signals. Alternative RD_WR and ENB signaling is also supported,

similar to the multiplexed example in Section 9.4.4.3, "RD_WR / ENB Control Mode Examples". The HBI read/

write mode is selectable via the HBI_rw_mode_strap. The polarities of the RD_WR and ENB signals are select-

able via the HBI_rd_rdwr_polarity_strap, and HBI_wr_en_polarity_strap.

• When accessing internal registers or FIFOs in 16 and 8-bit modes, consecutive address cycles must be within the

same DWORD until the DWORD is completely accessed (some internal registers are excluded from this require-

ment). Although BYTEs and WORDs can be accessed in any order, the diagrams in this section depict accessing

the lower address BYTE or WORD first.

9.5.6.1

Configuration Register Data Access

The figures in this section detail configuration register read and write operations in indexed address mode for 16 and 8-

bit modes.

16-BIT READ AND WRITE

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