STM32F413CG datasheet(139/207 Pages) STMICROELECTRONICS

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STM32F413xG/H

Electrical characteristics

174

SAI characteristics

Unless otherwise specified, the parameters given in Table 68 for SAI are derived from tests

performed under the ambient temperature, fPCLKx frequency and VDD supply voltage

conditions summarized in Table 16, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

•

Capacitive load C=30 pF

•

Measurement points are performed at CMOS levels: 0.5VDD

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate

function characteristics (SCK,SD,WS).

Table 68. SAI characteristics(1)

Symbol

Parameter

Conditions

Min

Max

Unit

fMCKL

SAI Main clock output

256 * 8K

256 * Fs(2)

MHz

FSCK

SAI clock frequency

Master data: 32 bits

128 * Fs

MHz

Slave data: 32 bits

128 * Fs

tv(FS)

FS valid time

Master mode

2.7 V <= VDD <= 3.6 V

-19

Master mode

1.71 V <= VDD <= 3.6 V

-28

th(FS)

FS hold time

Master mode

Slave mode

tsu(FS)

FS setup time

Slave mode

tsu(SD_ A_MR)

Data input setup time

Master receiver

0.5

tsu(SD_B_SR)

Slave receiver

1.5

th(SD_ A_MR)

Data input hold time

Master receiver

th(SD_B_SR)

Slave receiver

2.5

tv(SD_B_ST) Data output valid time

Slave transmitter (after enable edge)

2.7 V <= VDD <= 3.6 V

-15

Slave transmitter (after enable edge)

1.71 V <= VDD <= 3.6 V

-28

th(SD_B_ST) Data output hold time

Slave transmitter (after enable edge)

tv(SD_A_MT) Data output valid time

Master transmitter (after enable edge)

2.7 V <= VDD <= 3.6 V

-15

Master transmitter (after enable edge)

1.71 V <= VDD <= 3.6 V

-29

th(SD_A_MT) Data output hold time Master transmitter (after enable edge)

1. Guaranteed by characterization results.

2. 256 * Fs maximum corresponds to 45 MHz (APB2 maximum frequency)

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