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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PC87373 датащи(PDF) 145 Page - National Semiconductor (TI) |
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PC87373 датащи(HTML) 145 Page - National Semiconductor (TI) |
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145 / 174 page  12.0 Legacy Functional Blocks (Continued) 145 www.national.com Revision 1.1 12.3 UART FUNCTIONALITY (SERIAL PORT 1 AND SERIAL PORT 2) 12.3.1 General Description The Serial Port (SP) provides UART functionality. The generic SP supports serial data communication with a remote periph- eral device or modem, using a wired interface. The functional block can function as a standard NS16450 or NS16550A or as an Extended UART. 12.3.2 UART Register Bank Overview Four register banks, each containing eight registers, control UART operation. All registers use the same 8-byte address space to indicate offsets 00h through 07h. The Bank Select Register (BSR) selects the active bank and is common to all banks (see Figure 42). Figure 42. UART Register Bank Architecture 12.3.3 SP1 and SP2 Register Maps All registers are VDD3 powered. Table 58. Bank 0 Register Map Offset Mnemonic Register Name Type 00h RXD Receiver Data Port RO 00h TXD Transmitter Data Port W 01h IER Interrupt Enable R/W 02h EIR Event Identification (Read Cycles) RO FCR FIFO Control (Write Cycles) W 03h LCR1 1. When bit 7 of this register is set to 1, bits 6–0 of BSR select the bank. Line Control R/W BSR1 Bank Select 04h MCR Modem/Mode Control R/W 05h LSR Link Status RO 06h MSR Modem Status RO 07h SPR/ASCR Scratchpad/Auxiliary Status and Control R/W BANK 0 BANK 1 BANK 2 BANK 3 Offset 07h Offset 06h Offset 05h Offset 04h LCR/BSR Offset 02h Offset 01h Offset 00h Common Register Throughout All Banks 16550 Banks UART Banks (Banks 0-3) |
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