GXM datasheet(224/244 Pages) NSC

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Revision 3.1

Instruction Set (Continued)

9.4

FPU INSTRUCTION SET

The processor core is functionally divided into the FPU,

and the integer unit. The FPU processes floating point

instructions only and does so in parallel with the integer

unit.

For example, when the integer unit detects a floating point

instruction without memory operands, after two clock

cycles the instruction passes to the FPU for execution.

The integer unit continues to execute instructions while

the FPU executes the floating point instruction. If another

FPU instruction is encountered, the second FPU instruc-

tion is placed in the FPU queue. Up to four FPU instruc-

tions can be queued. In the event of an FPU exception,

while other FPU instructions are queued, the state of the

CPU is saved to ensure recovery.

The instruction set for the FPU is summarized in Table 9-

29 on page 225. The table uses abbreviations that are

described in Table 9-28.

Table 9-28. FPU Instruction Set Table Legend

Abbr.

Description

Stack register number

TOS

Top of stack register pointed to by SSS in the

status register.

ST(1)

FPU register next to TOS

ST(n)

A specific FPU register, relative to TOS

M.WI

16-bit integer operand from memory

M.SI

32-bit integer operand from memory

M.LI

64-bit integer operand from memory

M.SR

32-bit real operand from memory

M.DR

64-bit real operand from memory

M.XR

80-bit real operand from memory

M.BCD

18-digit BCD integer operand from memory

FPU condition code

Env Regs

Status, Mode Control and Tag Registers,

Instruction Pointer and Operand Pointer

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