GXM datasheet(208/244 Pages) NSC

208 / 244 page

www.national.com

208

Revision 3.1

Instruction Set (Continued)

9.2

CPUID INSTRUCTION

The CPUID instruction (opcode 0FA2) allows the software

to make processor inquiries as to the vendor, family,

model, stepping, features and also provides cache infor-

mation. The GXm with MMX supports both the standard

and National Semiconductor extended CPUID levels.

The presence of the CPUID instruction is indicated by the

ability to change the value of the ID Flag, bit 21 in the

EFLAGS register.

The CPUID level allows the CPUID instruction to return

different information in the EAX, EBX, ECX, and EDX reg-

isters. The level is determined by the initialized value of

the EAX register before the instruction is executed. A

summary of the CPUID levels is shown in Table 9-16.

9.2.1

Standard CPUID Levels

The standard CPUID levels are part of the standard x86

instruction set.

9.2.1.1

CPUID Instruction with EAX = 00000000h

Standard function 0h (EAX = 0) of the CPUID instruction

returns the maximum standard CPUID levels as well as

the processor vendor string.

After the instruction is executed, the EAX register contains

the maximum standard CPUID levels supported. The

maximum standard CPUID level is the highest acceptable

value for the EAX register input. This does not include the

extended CPUID levels.

The EBX through EDX registers contain the vendor string

of the processor as shown in Table 9-17.

9.2.1.2

CPUID Instruction with EAX = 00000001h

Standard function 01h (EAX = 1) of the CPUID instruction

returns the processor type, family, model, and stepping

information of the current processor in the EAX register

(see Table 9-18). The EBX and ECX registers are

reserved.

The standard feature flags supported are returned in the

EDX register as shown in Table 9-19 on page 209. Each

flag refers to a specific feature and indicates if that feature

is present on the processor. Some of these features have

protection control in CR4. Before using any of these fea-

tures on the processor, the software should check the cor-

responding feature flag. Attempting to execute an

unavailable feature can cause exceptions and unexpected

behavior. For example, software must check bit 4 before

attempting to use the Time Stamp Counter instruction.

Table 9-16. CPUID Levels Summary

CPUID

Type

Initialized

EAX

Returned Data in EAX, EBX,

ECX, EDX Registers

Standard

00000000h

Maximum standard levels, CPU

vendor string

Standard

00000001h

Model, family, type and features

Standard

00000002h

TLB and cache information

Extended

80000000h

Maximum extended levels

Extended

80000001h

Extended model, family, type and

features

Extended

80000002h

CPU marketing name string

Extended

80000003h

Extended

80000004h

Extended

80000005h

TLB and L1 cache description

Table 9-17. CPUID Data Returned when EAX = 0

(Note)

Returned Contents

Description

EAX

Maximum Standard

Level

EBX

7943

(iryC)

Vendor ID String 1

EDX

4978

(snlx)

Vendor ID String 2

ECX

6574

(daet)

Vendor ID String 3

Note: The register column is intentionally out of order.

Table 9-18. EAX, EBX, ECX CPUID Data

Returned when EAX = 1

Returned

Contents

Description

EAX[3:0]

Stepping ID

EAX[7:4]

Model

EAX[11:8]

Family

EAX[15:12]

Type

EAX[31:16]

Reserved

EBX

Reserved

ECX

Reserved

GXM датащи(PDF) 208 Page - National Semiconductor (TI)

GXM датащи(HTML) 208 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL