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GXM датащи(PDF) 176 Page - National Semiconductor (TI) |
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GXM датащи(HTML) 176 Page - National Semiconductor (TI) |
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176 / 244 page ![]() www.national.com 176 Revision 3.1 Power Management (Continued) 6.5.2 Initiating Suspend with HALT The CPU also enters Suspend mode as a result of execut- ing a HALT instruction if the SUSP_HALT bit in CCR2 (Index C2h[3]) is set. Suspend mode is then exited upon recognition of an NMI, an unmasked INTR, or an SMI#. Normally SUSPA# is deactivated within six SYSCLKS from the detection of an active interrupt. However, the deactivation of SUSPA# may be delayed until the end of an active refresh cycle. The CPU also allows PCI accesses during a HALT-initi- ated Suspend mode. If the CPU is in the middle of a PCI access when the Halt instruction is executed, the asser- tion of SUSPA# will be delayed until the PCI access is completed. Figure 6-2. HALT-Initiated Suspend Mode SYSCLK FRAME# C/BE[3:0]# AD[15:0] IRDY# INTR, NMI, SUSPA# O X I I X X SMI# HALT |
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