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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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GXM датащи(PDF) 161 Page - National Semiconductor (TI) |
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GXM датащи(HTML) 161 Page - National Semiconductor (TI) |
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161 / 244 page  Revision 3.1 161 www.national.com Integrated Functions (Continued) Index 44h PCI Arbitration Control 2 Register (R/W) Default Value = 00h 7PP Ping-Pong: 0 = Arbiter grants the processor bus per the setting of bits [2:0]. 1 = Arbiter grants the processor bus ownership of the PCI bus every other arbitration cycle. 6:4 FAC Fixed Arbitration Controls: These bits control the priority under fixed arbitration. The priority table is as follows (priority listed highest to lowest): 000 = REQ0#, REQ1#, REQ2# 001 = REQ1#, REQ0#, REQ2# 010 = REQ0#, REQ2#,REQ1# 011 = Reserved 100 = REQ1#, REQ2#, REQ0# 101 = Reserved 110 = REQ2#, REQ1#, REQ0# 111 = REQ2#, REQ0#, REQ1# Note: The rotation arbitration bits [2:0] must be set to 000 for full fixed arbitration. If rotation bits are not set to 000, then hybrid arbitration will occur. If Ping-Pong is enabled (bit 7 = 1), the processor will have priority every other arbitration. In this mode, the arbiter grants the PCI bus to a master and ignores all other requests. When the master finishes, the processor will be guaranteed access. At this point PCI requests will again be recognized. This will switch arbitration from CPU-to-PCI to CPU-to-PCI, etc. 3RSVD Reserved: Set to 0. 45h-FFh -- Reserved Table 4-40. PCI Configuration Registers (Continued) Bit Name Description |
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