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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M38B53M4-059FP датащи(PDF) 156 Page - Mitsubishi Electric Semiconductor |
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M38B53M4-059FP датащи(HTML) 156 Page - Mitsubishi Electric Semiconductor |
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156 / 355 page  2-68 38B5 Group User’s Manual APPLICATION 2.3 Serial I/O The communication is performed according to the timing shown in Figure 2.3.45. In the slave unit, when a synchronous clock is not input within a certain time (heading adjusment time), the next clock input is processed as the beginning (heading) of a block. When a clock is input again after one block (8 bytes) is received, the clock is ignored. Figure 2.3.46 shows the relevant registers setting in the master unit and Figure 2.3.47 shows the relevant registers setting in the slave unit. Fig. 2.3.45 Timing chart Fig. 2.3.46 Relevant registers setting in master unit D0 Byte cycle Block transfer term Block transfer cycle D1 D2 D7 D0 Interval between blocks Processing for heading adjustment Heading adjustment time 0 P55/TxD pin: CMOS output BRG clock: f(XIN) Serial I/O2 clock: SCLK21 UARTCON Serial I/O2 control register (address 001D16) 1 1 1 1 1 0 0 0 SIO2CON BRG 0716 0 0 Master unit BRG count source : f(XIN) Synchronous clock : BRG/4 SRDY2 output disabled Transmit interrupt source : Transmit shift operating completion Transmit enabled Receive enabled Clock synchronous serial I/O Serial I/O2 enabled UART control register (address 001716) Baud rate generator (address 001616) Set “division ratio – 1” |
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