PC87591L datasheet(215/437 Pages) NSC

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Embedded Controller Modules (Continued)

Revision 1.07

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ACM Timing Control Register (ACMTIM)

This register controls the sampling delay for the voltage level and compare out data; it also controls the division of the trigger

signal. ACMTIM is set to 3716 on reset.

Location: 00 FD4416

Type: R/W

Bit

76543210

Name

Reserved

T0DIV

Reserved

SMPDLY

Reset

110111

Bit

Description

2-0

SMPDLY (Data Sampling Delay). Compensates for the settling time of the D/A converter and the input

comparators. To calculate the required delay value, see “Sampling Delay” on page 210.

Bits

Settling Compare

Max

2 1 0 Period1

Period1 Core Freq2

0 0 0:

5.5MHz

0 0 1:

8.5 MHz

0 1 0:

11.5 MHz

0 1 1:

14.2 MHz

1 0 0:

16.5 MHz

1 0 1:

20.0 MHz

1 1 0:

20.0 MHz

1 1 1:

20.0 MHz (default)

___________________________

1. The Settling and Compare periods are in clock cycles.

2. Conversion step time is equal to Settling Period + Compare Period

Reserved.

5-4

T0DIV (Trigger Signal Division Factor). Controls the division of the T0IN trigger signal in Low Power Threshold

Comparison mode. A higher division factor gives a lower power consumption in Idle operation mode (see

Section 4.17 on page 235). T0IN frequency is separately set (see Section 4.10 on page 164).

Bits

5 4

T0In Division Factor

0 0:

0 1:

1 0:

1 1:

128 (default)

7-6

Reserved.

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