TMS320DM647 datasheet(110/190 Pages) TI1

110 / 190 page

DM648

TMS320DM647

TMS320DM648

SPRS372H – MAY 2007 – REVISED APRIL 2012

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Table 6-39. DQS and DQ Routing Specification (1) (continued)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

Center to center DQ to other DDR2 trace spacing(2) (6)

4 w

Center to Center DQ to other DQ trace spacing(7) (2)

DQ/DQS E Skew Length Mismatch(3) (4) (5)

100

Mils

(6)

DQs from other DQS domains are considered other DDR2 trace.

(7)

DQLM is the longest Manhattan distance of each of the DQS and DQ net classes.

Figure 6-18 shows the routing for the DQGATE net classes. Table 6-40 contains the routing specification.

DM648 is shown in this figure as an example of the device and represents the entire set of devices that include:

DM647/DM648.

Figure 6-18. DQGATE Routing

Table 6-40. DQGATE Routing Specification

NO.

PARAMETER

MIN

TYP

MAX

UNIT

DQGATEL Length F(1)

CKB0B1

DQGATEH Length F(2) (3)

CKB2B3

Center to center DQGATE to any other trace spacing

4 w

DQS/DQ nominal trace length

DQLM - 50

DQLM

DQLM +

Mils

DQGATEL Skew(4)

100

Mils

DQGATEH Skew(5) (3)

100

Mils

(1)

CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets.

(2)

CKB2B3 is the sum of the length of the CK net plus the average length of the DQS2 and DQS3 nets.

(3)

Only used on 32-bit-wide DDR2 memory systems.

(4)

Skew from CKB0B1

(5)

Skew from CKB2B3

110

Peripheral Information and Electrical Specifications

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