CS5530 datasheet(163/241 Pages) NSC

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Index 87h

Second Level Power Management Status Mirror Register 4 (RO)

Reset Value = 00h

GPIO2 SMI Status (Read Only): SMI was caused by transition on (properly-configured) GPIO2 pin?

0= No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 92h[2].

GPIO1 SMI Status (Read Only): SMI was caused by transition on (properly-configured) GPIO1 pin?

0= No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 92h[1].

GPIO0 SMI Status (Read Only): SMI was caused by transition on (properly-configured) GPIO0 pin?

0= No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 92h[0].

Lid Position (Read Only): This bit maintains the current status of the lid position. If the GPIO6 pin is configured as the lid

switch indicator, this bit reflects the state of the pin.

Lid Switch SMI Status (Read Only): SMI was caused by a transition on the GPIO6 (lid switch) pin?

0= No; 1 = Yes.

For this to happen, the GPIO6 pin must be configured both as an input (F0 Index 90h[6] = 0) and

as the lid switch (F0 Index 92h[6] =1).

Codec SDATA_IN SMI Status (Read Only): SMI was caused by AC97 codec producing a positive edge on SDATA_IN?

0= No; 1 = Yes.

This is the second level of status is reporting. The top level status is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 80h[5].

RTC Alarm (IRQ8) SMI Status (Read Only): SMI was caused by an RTC interrupt? 0 = No; 1 = Yes.

This SMI event can only occur while in 3V Suspend and RTC interrupt occurs.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

ACPI Timer SMI Status (Read Only): SMI was caused by an ACPI Timer MSB toggle? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation configuration is at F0 Index 83h[5].

Notes:

Properly-configured means that the GPIO pin must be enabled as a GPIO (if multiplexed pin), an input, and to cause an

SMI.

This register provides status on several miscellaneous power management events that generate SMIs, as well as the sta-

tus of the Lid Switch. It is called a Mirror register since an identical register exists at F0 Index F7h. Reading this register

does not clear the status, while reading its counterpart at F0 Index F7h does clear the status.

Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

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