CS5530 datasheet(129/241 Pages) NSC

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Functional Description (Continued)

3.8.2

Video Accelerator

The CS5530 off-loads the processor from several comput-

ing-intensive tasks related to the playback of full motion

video. By incorporating this level of hardware-assist, a

CS5530/GXLV processor based system can sustain 30

frames-per-second of MPEG quality video.

3.8.2.1

Line Buffers

The CS5530 accepts an 8-bit video stream from the pro-

cessor and provides three full MPEG resolution line buff-

ers (3x360x32-bit). MPEG source horizontal resolutions

up to 720 pixels are supported. By having three line buff-

ers, the display pipeline can read from two lines while the

next line of data is being loaded from the processor. This

minimizes memory bandwidth utilization by requiring that

a source line be transferred only once per frame. Peak

bandwidth is also reduced by requiring that the video

source line be transferred within the horizontal line time

rather than forcing the transfer to occur during the active

video window. This efficient utilization of memory band-

width allows the processor and graphics accelerator an

increased opportunity to access the memory subsystem

and improves overall system performance during video

playback.

3.8.2.2

Video Port Protocol

The video port operates at one-half the processor’s core

clock rate and utilizes a two-wire handshake protocol. The

VID_VAL input signal indicates that valid data has been

placed on the VID_DATA[7:0] bus. When the CS5530 is

ready to accept data, it asserts VID_RDY to indicate that a

linebufferisfreetoaccept thenextline. When both

VID_VAL

and

VID_RDY

are

asserted,

VID_DATA

advances.

The VID_RDY signal is driven by the CS5530 one clock

early to the processor while the VID_VAL signal is driven

by the processor coincident with valid data on VID_DATA.

A sample timing diagram is shown in Figure 3-24.

Figure 3-24. Video Port Protocol

VID_CLK

VID_VAL

8CLKs

8 + 2CLKs

VID_RDY

2CLKs

3CLKs

VID_DATA[7:0]

8CLKs

Note: VID_CLK = CORE_CLK/2

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