MB91F587LD datasheet(149/177 Pages) SPANSION

149 / 177 page

D at aS h ee t

146

MB91F587LA_DS705-00012-2v0-E, August 22, 2014

CONFIDENTIAL

(4-4) I2C timing (SMR:MD2-0="100"b)

(TA: Recommended operating conditions, VCC=5.0V±10%, VSS=AVSS=0.0V)

Parameter

Symbol

Pin name

Conditions

Standard

mode

High-speed

mode*3

Unit Remarks

Min Max Min

Max

SCL clock

frequency

fSCL

SCK0,SCK1,

SCK3,SCK4,

SCK3_1,SCK4_1

(SCL)

CL=50pF

R=(VP/IOL)

100

400

kHz

"Repeat START

condition"

hold time

SDA ↓ → SCL ↓

tHDSTA

SCK0,SCK1,

SCK3,SCK4,

SCK3_1,SCK4_1

(SCL)

SOT0,SOT1,

SOT3,SOT4,

SOT3_1,SOT4_1

(SDA)

4.0

0.6

µs

"L" width

for SCL clock

tLOW

SCK0,SCK1,

SCK3,SCK4,

SCK3_1,SCK4_1

(SCL)

4.7

1.3

µs

"H" width

for SCL clock

tHIGH

4.0

0.6

µs

"Repeat START

condition"

setup time

SCL ↑ → SDA ↓

tSUSTA

SCK0,SCK1,

SCK3,SCK4,

SCK3_1,SCK4_1

(SCL)

SOT0,SOT1,

SOT3,SOT4,

SOT3_1,SOT4_1

(SDA)

4.7

0.6

µs

Data hold time

SCL ↓ → SDA ↓ ↑ tHDDAT

3.45

0.90

µs

Data setup time

SDA ↓ ↑ → SCL ↑ tSUDAT

250

100

"STOP condition"

setup time

SCL ↑ → SDA ↑

tSUSTO

4.0

0.6

µs

Bus free time

between "STOP

condition" and

"START condition"

tBUF

4.7

1.3

µs

Noise filter

tSP

2tCPP

*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA output lines, respectively.

VP shows that the power supply voltage of the pull-up resistor and IOL shows the VOL guarantee current.

*2: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal.

*3: A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device

satisfies the requirement of "tSUDAT ≥ 250 ns".

*4: tCPP is the peripheral clock cycle time. Adjust the clock of the peripheral bus to 8MHz or more when use I2C.

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