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MB91F587LD датащи(PDF) 140 Page - SPANSION

номер детали MB91F587LD
подробное описание детали  This document states the current technical specifications regarding
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D at aS h ee t
August 22, 2014, MB91F587LA_DS705-00012-2v0-E
137
CONFIDENTIAL
(4-1-5) When the serial chip select is used (SCSCR:CSEN=1)
• Serial clock output signal detect level "H"(SMR,SCSFR:SCINV=0)
• Serial chip select inactive level "H"(SCSCR,SCSFR:CSLVL=1)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Parameter
Symbol
Pin name
Conditions
Value
Unit Remarks
Min
Max
SCS ↓ ⇒ SCK ↓
setup time
tCSSI
SCK1 to SCK4,
SCK3_1,SCK4_1,
SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
Master mode
CL=50pF
tCSSU*1+0
tCSSU*1+50
ns
SCK ↑ ⇒ SCS ↑
hold time
tCSHI
tCSHD*2-50
tCSHD*2+0
ns
SCS
deselect time
tCSDI
SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
-50+5tCPP
+tCSDS*3
+50+5tCPP
+tCSDS*3
ns
SCS ↓ ⇒ SCK ↓
setup time
tCSSE
SCK1 to SCK4,
SCK3_1,SCK4_1,
SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
Slave mode
CL=50pF
3tCPP+30
-
ns
SCK ↑ ⇒ SCS ↑
hold time
tCSHE
0
-
ns
SCS
deselect time
tCSDE
SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
3tCPP+30
-
ns
SCS ↓ ⇒ SOT
delay time
tDSE
SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1,
SOT0 to SOT4,
SOT3_1,SOT4_1
-
40
ns
SCS ↑ ⇒ SOT
delay time
tDEE
0
-
ns
SCK ↓ ⇒ SCS ↓
clock switch time
tSCC
SCK1 to SCK4,
SCK3_1,SCK4_1,
SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
Master mode
round
operation
CL=50pF
3tCPP+0
3tCPP+50
ns
*1: tCSSU =SCSTR:CSSU7-0 × Serial chip select timing operation clock
*2: tCSHD=SCSTR:CSHD7-0 × Serial chip select timing operation clock
*3: tCSDS=SCSTR:CSDS15-0 × Serial chip select timing operation clock
For details of *1, *2 and *3 above, see Hardware Manual.
Notes: • This is the AC characteristic in CLK synchronized mode.
•
CL is the load capacitance applied to pins during testing.
•
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.



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