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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MB91F587LD датащи(PDF) 134 Page - SPANSION |
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MB91F587LD датащи(HTML) 134 Page - SPANSION |
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134 / 177 page  D at aS h ee t August 22, 2014, MB91F587LA_DS705-00012-2v0-E 131 CONFIDENTIAL (4-1-2) Normal synchronous transfer (SCR:SPI=0) and serial clock output signal detect level "L"(SMR:SCINV=1) (TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Serial clock cycle time tSCYC SCK0 to SCK4, SCK3_1,SCK4_1 Master mode CL=50pF 4tCPP - ns SCK ↑ ⇒ SOT delay time tSHOVI SCK0 to SCK4, SCK3_1,SCK4_1, SOT0 to SOT4, SOT3_1,SOT4_1 -30 +30 ns Valid SIN ⇒ SCK ↓ setup time tIVSLI SCK0 to SCK4, SCK3_1, SCK4_1, SIN0 to SIN4, SIN3_1, SIN4_1 30 - ns SCK ↓ ⇒ Valid SIN hold time tSLIXI 0 - ns Serial clock "H" pulse width tSHSL SCK0 to SCK4, SCK3_1, SCK4_1 Slave mode CL=50pF tCPP+10 - ns Serial clock "L" pulse width tSLSH 2tCPP-10 - ns SCK ↑ ⇒ SOT delay time tSHOVE SCK0 to SCK4, SCK3_1,SCK4_1, SOT0 to SOT4, SOT3_1,SOT4_1 - 30 ns Valid SIN ⇒ SCK ↓ setup time tIVSLE SCK0 to SCK4, SCK3_1, SCK4_1, SIN0 to SIN4, SIN3_1, SIN4_1 10 - ns SCK ↓ ⇒ Valid SIN hold time tSLIXE 20 - ns SCK fall time tF SCK0 to SCK4, SCK3_1, SCK4_1 - 5 ns SCK rise time tR SCK0 to SCK4, SCK3_1, SCK4_1 - 5 ns Notes: • This is the AC characteristic in CLK synchronized mode. • CL is the load capacitance applied to pins during testing. • The maximum baud rate is limited by the internal operation clock used and other parameters. See Hardware Manual for details. |
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