поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

STM32F756VG датащи(PDF) 190 Page - STMicroelectronics

номер детали STM32F756VG
подробное описание детали  Up to 25 communication interfaces
PDF  228 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F756VG датащи(HTML) 190 Page - STMicroelectronics

Back Button STM32F756VG Datasheet HTML 186Page - STMicroelectronics STM32F756VG Datasheet HTML 187Page - STMicroelectronics STM32F756VG Datasheet HTML 188Page - STMicroelectronics STM32F756VG Datasheet HTML 189Page - STMicroelectronics STM32F756VG Datasheet HTML 190Page - STMicroelectronics STM32F756VG Datasheet HTML 191Page - STMicroelectronics STM32F756VG Datasheet HTML 192Page - STMicroelectronics STM32F756VG Datasheet HTML 193Page - STMicroelectronics STM32F756VG Datasheet HTML 194Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 190 / 228 page
background image
Electrical characteristics
STM32F756xx
190/228
DocID027589 Rev 4
5.3.28
Quad-SPI interface characteristics
Unless otherwise specified, the parameters given in Table 106 and Table 107 for Quad-SPI
are derived from tests performed under the ambient temperature, fAHB frequency and VDD
supply voltage conditions summarized in Table 17: General operating conditions, with the
following configuration:
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 20 pF
Measurement points are done at CMOS levels: 0.5 ₓ VDD
Refer to Section 5.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics.
Table 105. LPSDR SDRAM write timings(1)
1. Guaranteed by characterization results.
Symbol
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
2THCLK−0.5
2THCLK+0.5
ns
td(SDCLKL _Data)
Data output valid time
-
4
th(SDCLKL _Data)
Data output hold time
0
-
td(SDCLKL_Add)
Address valid time
-
3.5
td(SDCLKL-SDNWE)
SDNWE valid time
-
0.5
th(SDCLKL-SDNWE)
SDNWE hold time
0
-
td(SDCLKL- SDNE)
Chip select valid time
-
0.5
th(SDCLKL- SDNE)
Chip select hold time
0
-
td(SDCLKL-SDNRAS)
SDNRAS valid time
-
0.5
th(SDCLKL-SDNRAS)
SDNRAS hold time
0
-
td(SDCLKL-SDNCAS)
SDNCAS valid time
-
0.5
td(SDCLKL-SDNCAS)
SDNCAS hold time
0
-
Table 106. Quad-SPI characteristics in SDR mode(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Fck1/t(CK)
Quad-SPI clock
frequency
2.7 V
≤VDD<3.6 V
CL=20 pF
-
-
108
MHz
1.71 V<VDD<3.6 V
CL=15 pF
-
-
100



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com