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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPEAR320S-2 датащи(PDF) 103 Page - STMicroelectronics |
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SPEAR320S-2 датащи(HTML) 103 Page - STMicroelectronics |
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103 / 113 page  SPEAr320S Timing requirements Doc ID 022508 Rev 2 103/113 5.16.2 SPI slave mode timings 5.17 SPP timing characteristics This section describes the timing characteristics of the standard parallel port (SPP). Figure 36. SPP timing waveform 5.18 UART timing characteristics Figure 37. UART transmit and receive waveform Table 78. SSP timing characteristics (slave mode) Symbol Parameters Min Max Unit TSSP_CLK SSP_CLK_IN input clock period TPCLK*12 254*256*TPCLK ns TSSP_CLKHigh SSP_SCK high pulse TSSP_CLK/2 TSSP_CLKLow SSP_SCK low pulse TSSP_CLK/2 TSU Data input setup time 4*TPCLK TH Data input hold time 0 TD Data output delay 3*TPCLK 4*TPCLK tSTRB SPP_DATAx Valid data tDS tDV tSELIN SPP_SELINn SPP_STRBn SPP_ACKn tACK SPP_BUSY Data read by CPU tSA tSB tSELIN tINIT SPP_AUTOFDn Auto Line Feed (can be used as 9th data/parity bit) SPP_INITn B0 B1 Start bit UARTTXD UARTRXD Stop Bit B2-- - B7 Pbit tBIT tBIT tBIT tBIT |
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