EM341 datasheet(179/237 Pages) SILABS

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EM341

180

Rev 1.0

Table 10.8 describes the key ADC parameters measured on Silicon Labs’ EM341 reference design at 25 °C and

VDD_PADS at 3.0 V, for a sampling clock of 6 MHz. The single-ended measurements were done at finput = 7.7%

fNyquist; level = 1.2 V p-p swing centered on 1.5 V. The differential measurements were done at finput = 7.7%

fNyquist, level = 1.2 V p-p swing and a common mode voltage of 1.5 V.

Table 10.8. ADC Module Key Parameters for Input Buffer Enabled and 6 MHz Sampling

Parameter

Performance

ADC_PERIOD

Conversion Time (µs)

128

256

512

1024

2048

4096

Nyquist Freq (kHz)

93.8k

46.9k

23.4k

11.7k

5.86k

2.93k

1.47k

732

3 dB Cut-off (kHz)

56.6k

28.3k

14.1k

7.07k

3.54k

1.77k

884

442

INL (codes peak)1

0.055

0.032

0.038

0.07

0.123

0.261

0.522

1.028

INL (codes RMS)1

0.028

0.017

0.02

0.04

0.077

0.167

0.326

0.65

DNL (codes peak)1

0.028

0.017

0.02

0.04

0.077

0.167

0.326

0.65

DNL (codes RMS)1

0.01

0.006

0.007

0.008

0.013

0.023

0.038

ENOB

(from single-cycle test)

3.6

5.0

6.6

8.1

9.5

10.7

11.3

11.6

SNR (dB)

Single-Ended

Differential2

SINAD (dB)

Single-Ended

Differential2

SDFR (dB)

Single-Ended

Differential

THD (dB)

Single-Ended

Differential

–33

–42

–51

–59

–60

–66

–69

–68

–76

–68

–80

–68

–82

ENOB (from SNR)2

Single-Ended

Differential

3.6

5.1

6.6

8.1

9.5

10.5

10.7

10.9

11.3

11.5

ENOB (from SINAD)2

Single-Ended

Differential

3.6

5.0

5.1

6.5

6.6

8.0

9.4

9.5

10.3

10.6

10.7

11.3

10.7

11.4

Equivalent ADC Bits1

[15:9]

[15:8]

[15:7]

[15:6]

[15:5]

[15:4]

[15:3]

[15:2]

Notes:

1. INL and DNL are referenced to a LSB of the Equivalent ADC Bits shown in the last row of this table.

2. ENOB (effective number of bits) can be calculated from either SNR (signal to non-harmonic noise ratio) or SINAD

(signal-to-noise and distortion ratio).

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