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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC16C925T-S/CL датащи(PDF) 160 Page - Microchip Technology |
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PIC16C925T-S/CL датащи(HTML) 160 Page - Microchip Technology |
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160 / 182 page  PIC16C925/926 DS39544A-page 158 Preliminary 2001 Microchip Technology Inc. FIGURE 15-16: A/D CONVERSION TIMING TABLE 15-12: A/D CONVERSION REQUIREMENTS 131 130 132 BSF ADCON0, GO Q4 A/D CLK A/D DATA ADRES ADIF GO SAMPLE OLD_DATA SAMPLING STOPPED DONE NEW_DATA 134 9 8 7 ... ... 2 1 0 133 133 Param No. Sym Characteristic Min Typ† Max Units Conditions 130 TAD A/D clock period PIC16C925/926 1.6 —— µsTOSC based, VREF ≥ 3.0V PIC16LC925/926 3.0 —— µsTOSC based, VREF ≥ 2.0V PIC16C925/926 2.0 4.0 6.0 µs A/D RC Mode PIC16LC925/926 3.0 6.0 9.0 µs A/D RC Mode 131 TCNV Conversion time (not including S/H time) (Note 1) —— 12 TAD 132 TACQ Acquisition time (Note 2) 10 40 — — — µs µs The minimum time is the amplifier settling time. This may be used if the “new” input voltage has not changed by more than 1 LSb (i.e., 5 mV @ 5.12V) from the last sam- pled voltage (as stated on CHOLD). 134 TGO Q4 to A/D clock start — TOSC/2 —— If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 135 TSWC Switching from convert → sample time 1.5 —— TAD † Data in “Typ” column is at 5V, 25 °C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 10.1 for min. conditions. |
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