RM0312 datasheet(253/275 Pages) STMICROELECTRONICS

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RM0312

ProxSense™ (PXS)

273

Configuring the charge transfer sequence

The ProxSense clock can be prescaled (using PRESC[2:0] in the PXS_CKCR1 register)

which serves as the basis for generating the UP and PASS phases.

The lengths of the two phases can be independently configured using UPLEN[2:0] and

PASSLEN[2:0] (PXS_CKCR2). To allow additional flexibility, setting the bit INCPHASE

(PXS_CKCR1) causes each of the UP and PASS phase lengths to be increased by one half

of a ProxSense clock cycle.

The length of the non-overlap period (the deadtime between the UP and PASS phases) is

determined by ANADEAD (PXS_CKCR1). When ANADEAD = ‘0’, there is a one-half cycle

deadtime between the UP and PASS phases. When ANADEAD = ‘1’, the deadtime is

basically zero cycles with each of the UP and PASS cycles shorted by about 10 ns to ensure

non-overlapping. Setting ANADEAD to ‘1’ increases the UP phase by one full cycle.

In the reset configuration with bits ANADEAD and INCPHASE set to ‘0’ and bits UPLEN and

PASSLEN set to ‘1’, a charge transfer cycle lasts four tPXS. For instance, when PRESC[2:0]

= ‘111’, fPXS = 16 MHz and each charge transfer cycle lasts 250 ns.

22.5

ProxSense operations

22.5.1

PXS on/off control

The ProxSense is enabled and disabled by respectively setting and resetting the PXSEN bit

in the PXS_CR1 register. Before enabling the ProxSense, certain PXS registers must be

initialized as they are only writable when PXSEN = 0.

22.5.2

PXS initialization

Before writing in any of the PXS registers, the corresponding peripheral clock must be

enabled in the CLK_PCKENR1 register.

Initialization before enabling the ProxSense

After enabling the corresponding peripheral clock, the clock frequency in the PXS_CKCR1

recommended at this stage to select ANADEAD and INCPHASE in PXS_CKCR1.

The stabilization time, the conversion completion threshold, and the sample and hold

strength selection must be selected in PXS_CR3.

If the noise detection is used it must be enabled at this stage in the PXS_CR2 register.

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