RM0312 datasheet(160/275 Pages) STMICROELECTRONICS

160 / 275 page

16-bit general purpose timer (TIM2/TIM3)

RM0312

160/275

DocID022352 Rev 3

Note:

As the bits AOE, BKP, BKE and OSSI can be write-locked depending on the LOCK

configuration, it can be necessary to configure all of them during the first write access to the

TIMx_BKR register.

Note:

The state of the external I/O pins connected to the OCx channels depends on the OCx

channel state and the GPIO registers.

Bits 1:0 LOCK: Lock configuration

These bits offer a write protection against software errors.

00: LOCK OFF - No bits are write protected.

01: LOCK Level 1 = OISx bit in TIMx_OISR register and BKE/BKP/AOE bits in TIMx_BKR register

can no longer be written.

10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP bits in TIMx_CCERx registers, as long

as the related channel is configured in output through the CCxS bits) as well as the OSSR and OSSI

bits can no longer be written.

11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx

registers, as long as the related channel is configured in output through the CCxS bits) can no

longer be written.

Note: The LOCK bits can be written only once after the reset. Once the TIMx_BKR register has been

written, their content is frozen until the next reset.

Table 35. Output control bit for OCx channels with break feature

Control bits

OCx/OCx_EN output state

MOE

bit

OSSI

bit

CCxE

bit

Output Disabled (not driven by the timer)

OCx=CCxP, OCx_EN=0

OCx= OCxREF + Polarity ( OCxREF xor CCxP)

OCx_EN=1

Output Disabled (not driven by the timer)

OCx=OISx, OCx_EN=0

Off-State (output enabled with inactive state)

OCx=OISx, OCx_EN=1

RM0312 датащи(PDF) 160 Page - STMicroelectronics