RM0312 datasheet(134/275 Pages) STMICROELECTRONICS

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16-bit general purpose timer (TIM2/TIM3)

RM0312

134/275

DocID022352 Rev 3

The TIMx_CCRi registers can be programmed with or without preload registers using the

OCiPE bit in the TIMx_CCMRi register.

In output compare mode, the update event UEV has no effect on the OCiREF and OCi

output. The timing resolution is one count of the counter. Output compare mode can also be

used to output a single pulse.

Procedure:

Select the counter clock (internal, external, prescaler).

Write the desired data in the TIMx_ARR and TIMx_CCRi registers.

Set the CCiIE bit if an interrupt request is to be generated.

Select the output mode as follwos:

–

Write OCiM = 0b011 to toggle OCi output pin when CNT matches CCRi

–

Write OCiPE = 0 to disable preload register

–

Write CCiP = 0 to select active high polarity

–

Write CCiE = 1 to enable the output

Enable the counter by setting the CEN bit in the TIMx_CR1 register.

The TIMx_CCRi register can be updated at any time by software to control the output

waveform, provided that the preload register is not enabled (OCiPE=’0’, else TIMx_CCRi

shadow register will be updated only at the next update event UEV). An example is given in

Figure 56.

Figure 56. Output compare mode, toggle on OC1

17.5.7

PWM mode

Pulse Width Modulation mode allows you to generate a signal with a frequency determined

by the value of the TIMx_ARR register and a duty cycle determined by the value of the

TIMx_CCRi register.

The PWM mode can be selected independently on each channel (one PWM per OCi output)

by writing 0b110 (PWM mode 1) or 0b111 (PWM mode 2) in the OCiM bits in the

TIMx_CCMRi register. You must enable the corresponding preload register by setting the

OCiPE bit in the TIMx_CCMRi register, and optionally enable the auto-reload preload

As the preload registers are transferred to the shadow registers only when an update event

occurs, before starting the counter, you have to initialize all the registers by setting the UG

bit in the TIMx_EGR register.

OC1REF=OC1

TIMx_CNT

B200

B201

0039

TIMx_CCR1

003A

Write B201h in the CC1R register

Match detected on OCR1

Interrupt generated if enabled

003B

B201

003A

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