ADE7166_15 datasheet(133/152 Pages) AD

133 / 152 page

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Rev. B | Page 133 of

152

SERIAL PERIPHERAL INTERFACE (SPI)

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/

ADE7569 integrate a complete hardware serial peripheral

interface on-chip. The SPI is full duplex so that eight bits of data

are synchronously transmitted and simultaneously received.

This SPI implementation is double buffered, allowing users to

read the last byte of received data while a new byte is shifted in.

The next byte to be transmitted can be loaded while the current

byte is shifted out.

The SPI port can be configured for master or slave operation.

The physical interface to the SPI is via the MISO (P0.5/MISO),

MOSI (P0.4/MOSI/SDATA), SCLK (P0.6/SCLK/T0), and SS

(P0.7/SS/T1) pins, while the firmware interface is via the SPI

Configuration SFR 1 (SPIMOD1, Address 0xE8), the SPI

Configuration SFR 2 (SPIMOD2, Address 0xE9), the SPI

interrupt status SFR (SPISTAT, Address 0xEA), the SPI/I2C

transmit buffer SFR (SPI2CTx, Address 0x9A), and the SPI/I2C

receive buffer SFR (SPI2CRx, Address 0x9B).

Note that the SPI pins are shared with the I2C pins. Therefore, the

user can enable only one interface at a time. The SCPS bit in the

configuration SFR (CFG, Address 0xAF) selects which peripheral

is active.

SPI REGISTERS

Table 145. SPI SFR List

SFR Address

Mnemonic

R/W

Length (Bits)

Default

Description

0x9A

SPI2CTx

SPI/I2C transmit buffer (see Table 146).

0x9B

SPI2CRx

SPI/I2C receive buffer (see Table 147).

0xE8

SPIMOD1

R/W

0x10

SPI Configuration SFR 1 (see Table 148).

0xE9

SPIMOD2

R/W

SPI Configuration SFR 2 (see Table 149).

0xEA

SPISTAT

R/W

SPI/I2C interrupt status (see Table 150).

Table 146. SPI/I2C Transmit Buffer SFR (SPI2CTx, Address 0x9A)

Bit

Mnemonic

Default

Description

[7:0]

SPI2CTx

SPI or I2C transmit buffer. When the SPI2CTx SFR is written, its content is transferred to the transmit

FIFO input. When a write is requested, the FIFO output is sent on the SPI or I2C bus.

Table 147. SPI/I2C Receive Buffer SFR (SPI2CRx, Address 0x9B)

Bit

Mnemonic

Default

Description

[7:0]

SPI2CRx

SPI or I2C receive buffer. When SPI2CRx SFR is read, one byte from the receive FIFO output is

transferred to SPI2CRx SFR. A new data byte from the SPI or I2C bus is written to the FIFO input.

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